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high voltage input protection device preliminary technical data ADM1270 rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2014 analog devices, inc. all rights reserved. features controls supply voltages from 4 v to 60 v gate drive for low voltage drop reverse supply protection gate drive for p-channel fets in-rush current limiting control adjustable current limit foldback current limiting automatic retry or latch-off on current fault programmable current-limit timer for soa power-good and fault outputs analog uv and ov protection 16-lead 3x3mm lfcsp package 16-lead qsop package applications industrial modules battery powered/portable instrumentation general description the ADM1270 is a current limiting controller that is intended to provide inrush current limiting and overcurrent protection for modular or battery powered systems. when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. these transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. the ADM1270 is designed to control the in-rush current during powering on of a system via an external p-channel fet. functional block diagram 1v 1v gate drive/logic current limit control v cb timer on timeout i out current limit timer v cc /sense+ sense- gate timer ground uv ov rpfg flb ldo vcap ref select iset fault fb_pg en timer_off pwrgd figure 1. to protect the system from a reverse polarity input supply, there is a provision made to control an additional external p-channel fet. this feature is used to prevent reverse current flow that could damage the load or the ADM1270. the ADM1270 is available in a 3x3 16-lead lfcsp and a 16-lead qsop package. free datasheet http://
ADM1270 preliminary technical data rev. pre | page 2 of 23 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal characteristics .............................................................. 5 ? esd caution...................................................................................5 ? pin configuration and function descriptions ..............................6 ? typical performance characteristics ..............................................9 ? typical application circuit ........................................................... 14 ? theory of operation ...................................................................... 15 ? functional block diagram ............................................................ 16 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history free datasheet http://
preliminary technical data ADM1270 rev. pre | page 3 of 23 specifications v cc /v sense+ = 4 v to 60 v, v sense = (v sense+ ? v sense? ) = 0 v, t a = ?40c to +125c, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions/comments power supply operating voltage range v cc 4 60 v quiescent current i cc 360 500 a gate on uv pin input current i uv 100 na uv 5.5 v; t a = ?40c to +85c input current i uv 1 a uv 5.5 v; t a = ?40c to +125c uv threshold uv th 0.99 1.0 1.01 v uv falling uv threshold hysteresis uv hyst 50 60 70 mv uv glitch filter uv gf 4 7 s 50 mv overdrive uv propagation delay uv pd 5 8 s uv low to gate pull-down active ov pin input current i ov 100 na ov 5.5 v; t a = ?40c to +85c input current i ov 1 a ov 5.5 v; t a = ?40c to +125c ov threshold ov th 0.99 1.0 1.01 v ov rising ov threshold hysteresis ov hyst 20 30 40 mv ov glitch filter ov gf 0.5 1.5 s 50 mv overdrive ov propagation delay ov pd 1 2 s ov high to gate pull-up active sense? input current i sense- 40 80 a sense? = 60 v vcap pin internally regulated voltage undervoltage lockout rising undervoltage lockout falling undervoltage hysteresis v vcap uvlo rise uvlo fall uvlo hyst 3.546 3.0 3.6 210 3.654 3.4 v v v mv 0 a i vcap 100 a; c vcap = 1 f v cc rising v cc falling iset pin reference select threshold v isetrsth 2.55 2.6 2.65 v if v iset > v isetrsth , an internal 1 v reference (v clref ) is used internal reference v clref 2 v accuracies included in total sense voltage accuracies gain of current sense amplifier av csamp 40 v/v accuracies included in total sense voltage accuracies input current i iset 100 na v iset vcap v; t a = ?40c to +85c input current i iset 1 a v iset vcap v; t a = ?40c to +125c rpfg pin reverse protection fet gate drive voltage v rpfg 0 v vcc 10v v rpfg 10 12 14 v v rpfg = v cc C v rpfg ; 60 v v cc 14 v; i rpfg 5 a rpfg pull-dn (on) current i rpfgdn 7 10 13 a v rpfg = vcc v gate pin gate drive voltage v gate v gate = v cc C v gate 10 12 14 v 60 v v cc 14 v; i gate 5 a gate pull-dn (on) current i gatedn 20 25 30 a v gate = vcc v gate pull-up (off ) current i gateup regulation i gateup_reg ?45 ?60 ?75 a v gate 2 v; (sense+) ? (sense?) = 70 mv fault i gateup_flt ?7 ?13 ?20 ma v gate = 2 v current sense voltage sense voltage current limit (sense+ ? sense?) v sensecl 46 50 54 mv v iset > 2.65 v; v flb > 1.1 v; v gate = 3 v; i gate = 0 a free datasheet http://
preliminary technical data ADM1270 rev. pre | page 4 of 23 parameter symbol min typ max unit test conditions/comments foldback inactive v gate = 3 v; i gate = 0 a 62.5 mv v iset = 2.5 v; v flb > 1.35 v 50 mv v iset = 2 v; v flb > 1.1 v 25 mv v iset = 1 v; v flb > 0.57 v 8.5 12.5 16.5 mv v iset = 0.5 v; v flb > 0.3 v foldback active 6.0 10.0 14 mv v flb = 0 v; v gate = 3 v; i gate = 0 a 21.0 25.0 29.0 mv v iset > 2 v; v flb = 0.5 v; v gate = 3 v; i gate = 0 a circuit breaker offset v cbos 0.5 1 1.5 mv circuit breaker trip voltage, v cb = v sensecl ? v cbos severe overcurrent voltage threshold v senseoc 90 100 110 mv v iset > 2.65 v 20 25 30 mv v iset = 0.5 v glitch filter duration 0.5 1.5 s response time 2.0 3.5 s timer pin timer pull-up current i timerup ?18 ?20 ?22 a overcurrent fault; 0.2 v v timer 2 v timer high threshold v timerh 1.96 2.0 2.04 v timer low threshold v timerl 0.18 0.2 0.22 v timer_off pin por pull-up current i por ?18 ?20 ?22 a initial power-on reset; v timer_off = 1 v retry pull-up current i tmroff ?0.8 ?1 ?1.2 a after fault when gate is off; v timer_off = 1 v timer_off high threshold v tmroffh 1.96 2.0 2.04 v foldback (flb pin) input current i flb 100 na v flb 5.5 v; t a = ?40c to +85c input current i flb 1 a v flb 5.5 v; t a = ?40c to +125c feedbk_pg (fb_pg pin) pwrgd rising threshold v pgth 0.99 1.0 1.01 v fb_pg rising pwrgd threshold hysteresis pg hyst 20 30 40 mv input current i fbpg 100 na v fb_pg 5.5 v; t a = ?40c to +85c input current i fbpg 1 a v fb_pg 5.5 v; t a = ?40c to +125c power-good glitch filter pg gf 0.5 1.5 s 50 mv overdrive fault pin output low voltage v ol_fault 0.1 v i fault = 100 a 0.5 v i fault = 1 ma leakage current i fault 1 a v fault = 5.5 v; fault output high-z enable pin input high voltage input low voltage v ih v il 1.2 0.4 v v leakage current i en 1 a v en = 5.5 v pwrgd pin output low voltage v ol_pwrgd 0.1 v i pwrgd = = 100 a 0.5 v i pwrgd = 1 ma vcc for valid pwrgd 1.7 v i sink = 100 a; v ol_pwrgd = 0.4 v leakage current i pwrgd 1 a v pwrgd = 60 v; pwrgd output high-z free datasheet http://
preliminary technical data ADM1270 rev. pre | page 5 of 23 absolute maximum ratings table 2. parameter rating vcc/sense+ ?0.3 v to +66 v vcap ?0.3 v to +6 v uv ?0.3 v to +6 v ov ?0.3 v to +6 v iset ?0.3 v to vcap + 0.3v flb ?0.3 v to +6 v fb_pg ?0.3 v to +6 v timer_off ?0.3 v to vcap + 0.3v timer ?0.3 v to vcap + 0.3v fault ?0.3 v to +6 v enable ?0.3 v to +6 v pwrgd ?0.3 v to +66 v gate ?0.3 v to v cc + 0.3v sense? ?0.3 v to v cc + 0.3v rpfg ?0.3 v to v cc + 0.3v v sense (v sense+ ? v sense? ) 0.3 v continuous current into any pin 10 ma storage temperature range ?65c to +150c operating temperature range ?40c to +125c lead temperature, soldering (10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 16 lead 3x3 lfcsp tbd c/w 16 lead qsop tbd c/w esd caution free datasheet http://
preliminary technical data ADM1270 rev. pre | page 6 of 23 pin configuration and fu nction descriptions 112 11 10 9 8 7 6 5 4 3 2 exposed pad (bottom) 13 14 15 16 vcc/ sense+ sense - vcap uv ov top view pwrgd gnd fault timer iset enable timer_off fb_pg rpfg gate flb figure 2. lfcsp pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vcap internal regulated supply. place a capacitor with a value of 1 f or greater on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin voltage. 2 iset current limit. this pin allows the current-limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. to achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from vcap. an external reference can also be used. 3 uv undervoltage input pin. an ex ternal resistor divider is connected from th e supply to this pin to allow an internal comparator to detect whether th e supply is under the uv limit. 4 ov overvoltage input pin. an external resistor divider is conn ected from the supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. 5 enable enable pin. this pin is a digital logic input. this inp ut must be high to allow the ADM1270 controller to begin a power-up sequence. if this pin is held low, the ADM1270 is prevented from powering up. there is no internal pull-up on this pin. 6 fault fault output. this pin indicates th at the device has shut down due to an over current fault condition. the device can be configured for automatic retry after shut do wn by connecting this pin directly to the enable pin. 7 gnd ground pin. 8 timer timer pin. an external capacitor, c timer , sets an soa over current fault delay. the gate pin is pulled off when the voltage on the timer pin exceeds the upper threshold. 9 timer_off timer off pin. an external capacitor, c timer_off , sets an initial timing cycle delay and the soa off-time delay. after an soa over current fault has occurred, the gate pin is pulled off until the voltage on the timer_off pin exceeds the threshold. 10 fb_pg pwrgd feedback input pin. an external resistor divider is connected from the output voltage to this pin to allow an internal comparator to detect when the output voltage is above the pwrgd threshold. 11 flb foldback pin. a foldback resistor divider is placed from the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the foldback feature ensures that the power through the fet is not increased beyond the soa limits. 12 pwrgd power-good signal. used to indicate that the supply is within tolerance. this signal is based on the voltage present on the fb_pg pin. 13 gate gate output pin. this pin is the gate drive of an extern al p-channel fet. this pin is driven by the fet drive controller, which provides a pull-down current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held off when the supply is below uvlo. 14 sense? negative current sense input pin. a sense resistor betw een the sense+ pin and the sense? pin sets the analog free datasheet http://
preliminary technical data ADM1270 rev. pre | page 7 of 23 pin no. mnemonic description current limit. the hot swap operation of the ADM1270 cont rols the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. 15 vcc/sense+ positive supply input pin. an undervolta ge lockout (uvlo) circuit resets the device when a low supply voltage is detected. gate is held off when the supply is below uvlo. no sequencing is required. positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog curren t limit. the hot swap operation of the ADM1270 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). 16 rpfg reverse protection fet gate driver output. connect to the gate of the external reverse protection p-channel fet for low voltage drop operation. ep ep exposed pad. the exposed pad is located on the undersid e of the lfcsp package. solder the exposed pad to the printed circuit board (pcb) to improve thermal dissipa tion. the exposed pad can be connected to ground. fg_pg iset 2 15 4 3 14 5 13 12 vcap gate uv vcc/ sense+ 1 16 sense- pwrgd rfpg flb gnd en 7 6 11 8 10 9 ov fault timer_off timer figure 3. qsop pin configuration table 5. pin function descriptions pin no. mnemonic description 1 vcc/sense+ positive supply input pin. an undervolta ge lockout (uvlo) circuit resets the device when a low supply voltage is detected. gate is held off when the supply is below uvlo. no sequencing is required. positive current sense input pin. this pin connects to the main supply input. a sense resistor between the sense+ pin and the sense? pin sets the analog curren t limit. the hot swap operation of the ADM1270 controls the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). 2 rpfg reverse protection fet gate driver output. connect to the gate of the external reverse protection p-channel fet for low voltage drop operation. 3 vcap internal regulated supply. place a capacitor with a value of 1 f or greater on this pin to maintain good accuracy. this pin can be used as a reference to program the iset pin voltage. 4 iset current limit. this pin allows the current-limit threshold to be programmed. the default limit is set when this pin is connected directly to vcap. to achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from vcap. an external reference can also be used. 5 uv undervoltage input pin. an ex ternal resistor divider is connected from th e supply to this pin to allow an internal comparator to detect whether th e supply is under the uv limit. 6 ov overvoltage input pin. an external resistor divider is conn ected from the supply to this pin to allow an internal comparator to detect whether the supply is above the ov limit. 7 enable enable pin. this pin is a digital logic input. this inp ut must be high to allow the ADM1270 controller to begin a free datasheet http://
preliminary technical data ADM1270 rev. pre | page 8 of 23 pin no. mnemonic description power-up sequence. if this pin is held low, the ADM1270 is prevented from powering up. there is no internal pull-up on this pin. 8 fault fault output. this pin indicates th at the device has shut down due to an over current fault condition. the device can be configured for automatic retry after shut do wn by connecting this pin directly to the enable pin. 9 gnd ground pin. 10 timer timer pin. an external capacitor, c timer , sets an soa over current fault delay. the gate pin is pulled off when the voltage on the timer pin exceeds the upper threshold. 11 timer_off timer off pin. an external capacitor, c timer_off , sets an initial timing cycle delay and the soa off-time delay. after an soa over current fault has occurred, the gate pin is pulled off until the voltage on the timer_off pin exceeds the threshold. 12 fb_pg pwrgd feedback input pin. an external resistor divider is connected from the output voltage to this pin to allow an internal comparator to detect when the output voltage is above the pwrgd threshold. 13 flb foldback pin. a foldback resistor divider is placed from the source of the fet to this pin. foldback is used to reduce the current limit when the source voltage drops. the foldback feature ensures that the power through the fet is not increased beyond the soa limits. 14 pwrgd power-good signal. used to indicate that the supply is within tolerance. this signal is based on the voltage present on the fb_pg pin. 15 gate gate output pin. this pin is the gate drive of an extern al p-channel fet. this pin is driven by the fet drive controller, which provides a pull-down current to charge the fet gate pin. the fet drive controller regulates to a maximum load current by regulating the gate pin. gate is held off when the supply is below uvlo. 16 sense? negative current sense input pin. a sense resistor betw een the sense+ pin and the sense? pin sets the analog current limit. the hot swap operation of the ADM1270 cont rols the external fet gate to maintain the sense voltage (v sense+ ? v sense? ). this pin also connects to the fet drain pin. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 9 of 23 typical performance characteristics 3.55 3.57 3.59 3.61 3.63 3.65 -40'c -5'c 25'c 85'c 125'c tj ('c) vout (v) load = 100ua load=500ua load=1ma fig figure 4. v cap vs. temperature, different loads 3.59 3.595 3.6 3.605 3.61 0 0.2 0.4 0.6 0.8 1 iload (ma) vout (v) figure 5. v cap vs load current 3.59 3.595 3.6 3.605 3.61 0 1020304050 vin (v) vout (v) load=100ua load=500ua load=1ma figure 6. v cap vs input voltage, different loads 0 50 100 150 200 250 300 350 400 450 500 -40'c -5'c 25'c 85c 125c tj ('c) ground current (ua) load=100ua load=500ua load=1ma figure 7. supply current (i cc ) vs. temperature, different loads 380 382 384 386 388 390 392 394 396 398 400 0 0.2 0.4 0.6 0.8 1 iload (ma) ground current (ua) figure 8. supply current (i cc ) vs. load current 300 320 340 360 380 400 420 0 1020304050 vin (v) ground current (ua) load=100ua load=500ua load=1ma figure 9. supply current (i cc ) vs. supply voltage (v cc ), different loads free datasheet http://
preliminary technical data ADM1270 rev. pre | page 10 of 23 oc vs temperature and vin 0 2 4 6 8 10 12 14 16 18 20 -50 -30 -10 10 30 50 70 90 110 130 temperature oc threshold (ma) vin = 4.5 vin =6 vin = 10 figure 10. v cap over current limit vs temperature, different input voltage vgate vs temperature and input voltage 11 11.2 11.4 11.6 11.8 12 12.2 12.4 12.6 12.8 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) vgate voltage (v) 14v 25v 50v figure 11. gate voltage vs. temperature, different input voltage rfpg voltage vs temperature and input voltage 11 11.2 11.4 11.6 11.8 12 12.2 12.4 12.6 12.8 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) rfpg voltage (v) 14v 25v 50v figure 12. rfpg voltage vs. temperature, different input voltage rfpg pull-down current vs temperature and input voltage 8 8.2 8.4 8.6 8.8 9 9.2 9.4 9.6 9.8 10 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) rfpg current (ua) 14v 25v 50v figure 13. rfpg pull-down current vs. temperature, different input voltage v_isetrsth vs v_iset various input voltages temperature = 25c 0.045 0.05 0.055 0.06 0.065 0.07 2.5 2.52 2.54 2.56 2.58 2.6 2.62 2.64 2.66 2.68 2.7 v_iset votlage current sense voltage 4v 25v 50v figure 14. v isetrsth vs v iset , different input voltage v_isetrsth vs temperature vin = 4v 2.5 2.55 2.6 2.65 -60 -40 -20 0 20 40 60 80 100 120 140 temperature current sense voltage v_isetrsh figure 15. v isetrsth vs temperature, v in = 4v free datasheet http://
preliminary technical data ADM1270 rev. pre | page 11 of 23 v_isetrsth vs v_iset vin = 4v 0.045 0.05 0.055 0.06 0.065 0.07 2.5 2.52 2.54 2.56 2.58 2.6 2.62 2.64 2.66 2.68 2.7 v_iset votlage current sense voltage -40c -5c 25c 85c 125c figure 16. v isetrsth vs v iset , different temperature timer current vs temperature and input voltage -22 -21.5 -21 -20.5 -20 -19.5 -19 -18.5 -18 -45 -25 -5 15 35 55 75 95 115 135 temperature (deg c) timer current (ua) 4v 6v 10v 20v 50v figure 17. timer current vs temperature, different v in timer off current vs temperature and input voltage -1.5 -1.4 -1.3 -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -45 -25 -5 15 35 55 75 95 115 135 temperature (degc) timer current (ua) 4v 6v 10v 20v 50v figure 18. timeroff current vs temperature, different v in por timer off current vs temperature and input voltage -22 -21.5 -21 -20.5 -20 -19.5 -19 -18.5 -18 0 5 10 15 20 25 30 35 40 45 50 55 input voltage timer current (ua) -40c -5c 25c 85c 125c figure 19. por timeroff current vs v in , different temperature por timer off current vs temperature and input voltage -22 -21.5 -21 -20.5 -20 -19.5 -19 -18.5 -18 -45 -25 -5 15 35 55 75 95 115 135 temperature (degc) timer current (ua) 4v 6v 10v 20v 50v figure 20. . por timeroff current vs temperature, different v in 0 1 2 3 4 5 6 7 0.9 0.95 1 1.05 1.1 vgate ov input voltage ADM1270 ov threshold vs temperature ov input rise ov input fall figure 21. ov threshold vs ov input voltage free datasheet http://
preliminary technical data ADM1270 rev. pre | page 12 of 23 ADM1270 uv threshold vs temperature 0.95 1 1.05 1.1 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) volts 0 0.01 0.02 0.03 0.04 0.05 0.06 uv rise uv fall hysteresis figure 22. uv threshold vs temperature ADM1270 ov threshold vs temperature 0.9 0.95 1 1.05 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) volts 0 0.01 0.02 0.03 ov rise ov fall hysteresis figure 23. ov threshold vs temperature pg rising threshold vs temperature 0.98 0.985 0.99 0.995 1 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) pg rising threshold (v) 4v pg rise 25v pg rise 50v pg rise figure 24. pg rising threshold vs temperature, different v in pg falling threshold vs temperature 0.95 0.955 0.96 0.965 0.97 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) pg rising threshold (v) 4v pg fall 25v pg fall 50v pg fall figure 25. pg falling threshold vs temperature, different v in severe oc threshold vs temperature 0.1 0.102 0.104 0.106 0.108 -60 -40 -20 0 20 40 60 80 100 120 140 temperature severe oc threshold (v) 4v ov 25v oc 50v oc figure 26. severe oc threshold vs temperature, different v in vse nse v s flb different temperature, v in = 25v 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 flb ( v ) vsense (v) -40c -5c 25c 85c 125c figure 27. v sense vs flb, different temperatures free datasheet http://
preliminary technical data ADM1270 rev. pre | page 13 of 23 vsense vs iset different temperature, v in = 25v 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 00.511.522.533.5 iset (v) vsense (v) -40c -5c 25c 85c 125c figure 28. v sense vs iset, different temperatures oc input current vs temperature different vsense, v in = 25v 0 5 10 15 20 25 30 35 40 45 50 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (degc) oc input current (ua ) 10mv 20mv 30mv 40mv 50mv 60mv figure 29. oc input current vs temperature, different v sense oc input current vs v sense different temperature, v in = 25v 0 5 10 15 20 25 30 35 40 45 50 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 v sense (v) oc input current (ua ) -40c -5c 25c 85c 125c figure 30. oc input current vs v sense , different temperature timer threshold vs temperature different vin 1.98 2 2.02 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) timer threshold (v) 4v 50v figure 31. oc timer threshold vs temperature, different v in timer off threshold vs temperature different vin 1.97 1.99 2.01 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) timer threshold (v) 4v 50v figure 32. oc timer off threshol d vs temperature, different v in free datasheet http://
preliminary technical data ADM1270 rev. pre | page 14 of 23 typical application circuit 1v 1v gate drive/logic current limit control v cb timer on timeout i out current limit timer v cc /sense+ sense- gate timer ground uv ov rpfg r sense c timer vout vin q2 q1 load flb ldo vcap ref select iset fault fb_pg en c timer_off timer_off pwrgd r1 r2 r3 r4 r5 r8 r7 r9 figure 33. typical application circuit free datasheet http://
preliminary technical data ADM1270 rev. pre | page 15 of 23 theory of operation when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. these transient currents can cause permanent damage to connector pins, as well as voltage dips on the backplane supply that can reset other boards in the system. the ADM1270 is designed to control the in-rush current during the powering on of a system, allowing a board to be inserted into a live backplane by protecting it from excess currents. the ADM1270 is a current limiting controller that is intended to provide inrush current limiting and overcurrent protection for modular or battery powered systems. the voltage developed across a sense resistor in the power path is measured with a current sense amplifier via the vcc/sense+ and sense? pins. a default limit of 50 mv is set, but this limit can be adjusted, if required, using a resistor divider network from the vcap pin to the iset pin. the ADM1270 limits the current through the sense resistor by controlling the gate voltage of an external p-channel fet in the power path, via the gate pin. the sense voltage and, therefore, the load current is maintained below the preset maximum. the ADM1270 protects the external fet by limiting the time that the fet remains on while the current is at its maximum value. this current-limit time is set by the choice of capacitors connected to the timer pin and the timer_off pin. this helps to maintain the fet in its safe operating area (soa). in addition to the timer, there is a foldback pin that is used to provide additional fet protection. the current limit is linearly reduced by the voltage on the flb pin, so that for large vds voltage drops, the actual current limit used by the part is lower, again helping to ensure the fet is kept within its soa. a minimum voltage clamp is used to ensure that even if the flb voltage is 0 v, the current is never reduced to zero, which would otherwise prevent the device from powering up. the ADM1270 features overvoltage (ov) and undervoltage (uv) protection, programmed using external resistor dividers on the uv and ov pins. a pwrgd signal can be used to detect when the output supply is greater than a voltage programmed using an external resistor divider on the fb_pg pin. to protect the system from a reverse polarity input supply, there is a provision made to control an additional external p-channel fet with the rpfg pin. this feature allows for a low on- resistance, low voltage drop fet to be used in place of a diode to perform the same function, thus saving power losses and improving overall efficiency. the reverse voltage protection fet is intended to prevent negative input voltages that could damage the load or the ADM1270. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 16 of 23 functional block diagram 1v 1v gate drive/logic current limit control v cb timer on timeout i out current limit timer v cc /sense+ sense- gate timer ground uv ov rpfg flb ldo vcap ref select iset fault fb_pg en timer_off pwrgd figure 34. functional block diagram free datasheet http://
preliminary technical data ADM1270 rev. pre | page 17 of 23 powering the ADM1270 a supply voltage from 4 v to 60 v is required to power the ADM1270 via the vcc/sense+ pin. the vcc/sense+ pin provides the majority of the bias current for the device; the remainder of the current needed to control the gate drive and best regulate the v gs voltage is supplied by the sense- pin. current sense inputs the load current is monitored by measuring the voltage drop across an external current sense resistor, r sense (see figure 35). an internal current sense amplifier provides a gain of 40 to the voltage drop detected across r sense . the result is compared to an internal reference and is used by the hot swap control logic to detect an overcurrent condition. figure 35. hot swap current sense amplifier current-limit reference the current-limit reference voltage determines the load current at which the ADM1270 limits the current during an over- current event. this reference voltage is compared to the amplified current sense voltage to determine when the current limit threshold is reached. an internal current-limit refere nce selector block continuously compares the iset and flb (foldback) voltages to determine which voltage is the lowest at an y given time; the lowest voltage is used as the current-limit re ference. this ensures that the programmed current limit, iset, is used in normal operation, and that the foldback feature reduces the current limit when required during startup and/or fault conditions. 40x current limit v cc /sense+ sense- gate ground ldo vcap r sense q1 4v to 60v current limit control ref select iset flb 2v figure 36. current-limit refe rence selection the foldback voltage varies during different modes of operation and, therefore, is clamped to a minimum level of 200 mv. this is to prevent zero current flow due to the current limit being set too low. figure 37 provides an example of how the flb (foldback) and iset voltages interact during startup as the ADM1270 is turning on the fet and charging the load capacitance. depending on ho w the foldback feature is configured, the transition point ca n vary to ensure that the fet is being operated within the correct limits. 2v 0.2v iset v flb t current-limit reference figure 37. interaction of foldback and iset current limits setting the current limit (iset) the maximum current limit is part ially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. however, as currents become larger, the sense resistor value decreases for a given current sense voltage. choosin g an appropriate current sense resistor can be difficult due to the limited selection of low value resistors. the ADM1270 provides an adjustable current sense voltage limit to handle this issue. the device allows the user to program the required current sense voltage limit from 12.5 mv to 62.5 mv. the default value is 50 mv and is achieved by connecting the iset pin directly to the vcap pin. this configures the device free datasheet http://
preliminary technical data ADM1270 rev. pre | page 18 of 23 to use an internal 2 v reference, which results in 50 mv at the sense inputs (see figure 38). figure 38. fixed 50 mv current sense limit to program the sense voltage from 12.5 mv to 62.5 mv, an external resistor divider sets th e reference voltage on the iset pin (see figure 39 ). 40x current limit v cc /sense+ sense- gate ground ldo vcap r sense q1 4v to 60v current limit control ref select iset flb 2v figure 39. adjustable 12.5 mv to 62.5 mv current sense limit the vcap pin has a 3.6 v internally generated voltage that can be used to set a voltage at the iset pin. assuming that v iset equals the voltage on the iset pi n, select the resistor divider values to set the iset voltage as follows: v iset = v sense 50 where v sense is the current sense voltage limit. the vcap rail also can be used as the pull-up supply for setting other pins. in order to guarantee accuracy specifications, do not apply a load to the vcap pin greater than 100 a. foldback foldback is a method to actively reduce the current limit as the voltage drop across the fet increases. this keeps the power dissipation in the fet at a minimum during power-up, overcurrent, or short-circuit events. it also reduces the need to oversize the fet to accommodate worst-case conditions, resulting in board size and cost savings. the ADM1270 detects the voltag e drop across the fet by sensing output voltage through a resistor divider. this assumes that the supply voltage remains constant and within tolerance. the device, therefore, relies on the principle that the drain of the fet is at the maximum expected supply voltage, and that the magnitude of the output voltage is relative to that of the v ds of the fet. using a resistor divider from the output voltage to the flb pin, the relationship from v out , and thus v ds , to v flb can be derived. design the resistor divider to result in a voltage equal to v iset /2 when v out falls below the desired level. this should be well below the working tolerance of the supply rail. as v out continues to drop, the current-limit reference follows v flb because it is now the lowest voltage input to the current-limit reference selector block. this results in a reduction of the current limit and, therefore, the regulated load current. to prevent the current from decreasing to zero, a clamp activates when v flb reaches 200 mv. the current limit cannot drop below this level. to ensure that the soa characteristics of a particular fet are not violated, the minimum current for this clamp varies from design to design. however, the current-limit reference fixes this clamp at 200 mv, which equals 10 mv across the sense resistor. therefore, the main iset voltage can be adjusted to adjust the clamp to the required percentage current reduction. for example, if v iset equals 1.6 v, the clamp can be set at 25% of the maximum current. timer the timer pin handles the timing function with an external capacitor, c timer . the timer pin comparator threshold is v timerh (2.0 v) and the timing current source is a 20 a pull- up. these current and voltage levels, in combination with the user chosen value of c timer , determine the fault current-limit time and the on-time of the hot swap retry duty cycle. the timer pin capacitor value is determined using the following equation: c timer = ( t on 20 a)/ v timerh where t on is the time that the fet is allowed to spend in regulation at the current limit. the choice of fet is based on ma tching this time with the soa characteristics of the fet. foldback can also be used to simplify the selection. when the voltage across the sens e resistor reaches the circuit breaker trip voltage, v cb , the 20 a timer pull-up current is activated, and the ADM1270 begins to regulate the load current at the current limit. this initia tes a rising voltage ramp on the timer pin. if the sense voltage falls below this circuit breaker trip voltage before the timer pin reaches v timerh , the 20 a pull-up is disabled and the timer pin is discharged to gnd. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 19 of 23 the circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. there is a small circuit breaker offset, v cbos , which causes the timer to start a short time before the current reaches the defined current limit. however, if the overcurrent co ndition is continuous and the sense voltage remains above the ci rcuit breaker trip voltage, the 20 a pull-up remains active and the fet remains in regulation. this allows the timer pin to reach v timerh and initiate the gate shutdown and the fault pin is pulled low immediately. in latch-off mode, the timer pin is discharged to gnd when it reaches the v timerh threshold. the timer_off pin begins to charge up. while the timer_off pin is being pulled up, the hot swap controller remains off and cannot be turned back on and the fault pin remains low. when the voltage on the timer_off pin goes above the v tmroffh threshold, the hot swap controller can be re-enabl ed by toggling the enable pin from high to low and then high again. timer_off the timer_off pin handles two timing functions with an external capacitor, c timer_off . there is one timer_off pin comparator threshold at v tmroffh (2.0 v). there are two timing current sourcesl, a 20 a pull-up and a 1 a pull-up. these current and voltage levels, in combination with the user chosen value of c timer_off , determine the initial power-on reset time and also set the fault current-limit off time. when vcc is connected to the input supply, the internal supply (vcap) of the ADM1270 must charge up. vcap starts up and settles in a very short time, when the under-voltage lockout (uvlo) voltage is exceeded at vcap, the device emerges from reset. during this first short reset period, the gate and timer pins are both held low. the ADM1270 then goes through an initial timing cycle. the timer_off pin is pulled high with 20 a. when the timer_off pin reaches the v tmroffh threshold (2.0 v), the initial timing cycle is complete. this initial power-on reset duration is determined by the following equation: t initial = v tmroffh ( c timer_off /20 a) for example, a 100 nf capacitor results in a delay of approximately 10 ms. if the uv and ov inputs indicate that vcc is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot swap operation. at the completion of this initial power-on reset cycle, the timer_off pin is ready to perform a second function. when the voltage at the timer pin exceeds the fault current-limit time threshold voltage of v timerh (2.0 v), the 1 a pull-up current is activated on timer_off and c timer_off begins to charge. this initiates a voltage ramp on the timer_off pin. when the timer_off pin reaches v tmroffh , the timer_off fault current-limit off time is complete. this fault current-limit off time is determined by the following equation: t timer_off = v tmroffh ( c timer_off /1 a) for example, a 100 nf capacitor results in an off time of approximately 200 ms from the time timer exceeds v timerh to the time timer_off reaches v tmroffh . hot swap retry duty cycle the ADM1270 turns off the fet after an overcurrent fault and then uses the capacitor on the timer_off pin to generate a delay before automatically retrying the hot swap operation. to configure the ADM1270 for auto-retry mode, tie the fault pin to the enable pin. note that a pull-up resistor to vcap is required on the fault pin. when an overcurrent fault occurs, the capacitor on the timer pin charges with a 20 a pull-up current. when the timer pin reaches v timerh (2.0 v), the gate pin is pulled high turning off the fet. when the fault pin is tied to the enable pin for auto-retry mode, the timer_off pin begins to charge with a 1 a current source. when the the timer_off pin reaches v tmroffh (2.0 v), it automatically restarts the hot swap operation. the automatic retry duty cycle is set by the ratio of 1a/20a and the ratio of c timer /c timer_off . the retry duty cycle is set by the following equation: duty_cycle = (c timer 1 a)/( c timer_off 20 a) the value of the c timer and c timer_off capacitors determine the on and off time of this cycle, which are calculated as follows: t on = v timerh ( c timer /20 a) t off = v tmroffh ( c timer_off /1 a) a 100 nf capacitor on the timer pin gives an on time of 10 ms. a 100nf capacitor on the timer_off pin gives an off time of 200 ms. the device retries continuously in this manner and can be disabled manually by holding the enable pin low, or by disconnecting the fault pin. to prevent thermal stress in the fet, a capacitor on the timer_off pin can be used to extend the retry time to any desired level. gate and rpfg clamps the circuits driving the gate and rpfg pins are clamped to less than 14 v below the vcc/sense+ pin. these clamps ensure that the maximum v gs rating of the external fets is not exceeded. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 20 of 23 fast response to severe overcurrent the ADM1270 includes a separate, high bandwidth, current sense amplifier that is used to detect a severe overcurrent that is indicative of a short-circuit. the fast response time allows the ADM1270 to handle events of this type that could otherwise cause catastrophic damage if not detected, and dealt with very quickly. the fast response ci rcuit ensures that the ADM1270 can detect an overcurrent even t of approximately 200% of the normal current limit (iset) an d control the current within about 2 s. undervoltage and overvoltage the ADM1270 monitors the supply voltage for undervoltage (uv) and overvoltage (ov) conditions. the uv and ov pins are connected to the inputs of voltage comparators and compared to an internal 1 v voltage reference. figure 40 illustrates the voltage monitoring input connections. an external resistor network divides the supply voltage for monitoring. an undervoltage event is detected when the voltage connected to the uv pin falls below 1 v, and the fet is turned off with the 10 ma pull-up device. similarly, when an overvoltage event occurs and the voltage on the ov pin exceeds 1 v, the fet is turned off us ing the 10 ma pull-up device. 40x v cc /sense+ sense- gate ground ldo vcap r sense q1 4v to 60v uv ov gate drive/logic 1v 1v figure 40. undervoltage and overvoltage supply monitoring enable input the ADM1270 provides a dedicate d enable digital input pin. the enable pin allows the ADM1270 to remain off by using a hardware signal, even when the voltage on the uv pin is above 1.0 v and the voltage on the ov pin is less than 1.0 v. although the uv pin can be used to provide a digital enable signal, using the enable pin for this purpose keeps the ability to monitor undervoltage conditions. in addition to the conditions for the uv and ov pins, the ADM1270 enable input pin must be high for the device to begin a power-up sequence. a similar function can be achieved using the uv pin directly. alternatively, if the uv divider function is still required, the configuration shown in figure 41 can be used. d1 v in system control ADM1270 en uv r1 r2 figure 41. using the uv pin as an enable diode d1 prevents the external driver pull-up from affecting the uv threshold. select diode d1 using the following criteria: ( v f d1 ) + ( v ol en ) << 1.0 v ( i f = v in / r1 ) ensure that the en sink current does not exceed the specified v ol value. if the open-dra in device has no pull-up, the diode is not required. power good the power good (pwrgd) output can be used to indicate whether the output voltage is above a user-defined threshold and can, therefore, be consider ed good. the pwrgd output is set by a resistor divider connected to the fb_pg pin (see figure 42). figure 42. generation of pwrgd signal when the voltage at the fb_pg pin is above the 1 v threshold (indicating that the output voltage has risen), the open-drain pull-down is disabled, allowing pwrgd to be pulled high. the pwrgd pin is an open-drain ou tput that pulls low when the voltage at the fb_pg pin is lower than the 1 v threshold minus the hysteresis (power bad). hysteresis on the fb_pg pin is fixed at 30mv. pwrgd is guaranteed to be in a valid state for vcc 1.7 v. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 21 of 23 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.65 1.50 sq 1.45 091609-a 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.80 0.75 0.70 compliant to jedec standards mo-229. figure 43. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very, very thin quad (cp-16-27) dimensions shown in millimeters compliant to jedec standards mo-137-ab controlling dimensions are in i nches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 01-28-2008-a figure 44. 16-lead body, shrink small outline package [qsop] (rq-16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option brand code ADM1270acpz-r7 ?40c to +125c lfcsp cp16-27 lnq ADM1270arqz-r7 ?40c to +125c qsop rq-16 free datasheet http://
preliminary technical data ADM1270 rev. pre | page 22 of 23 model 1 temperature range package description package option brand code ADM1270cp-evalz evaluation board ADM1270rq-evalz evaluation board 1 z = rohs compliant part. free datasheet http://
preliminary technical data ADM1270 rev. pre | page 23 of 23 notes ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr12259-0-3/14(pre) free datasheet http://

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